As disclosed in the related application, programmable, processor-controlled data terminal equipment ("DTEs"), such as personal computers, workstations, and data terminals, are increasingly common throughout schools, work places, and society in general. In addition, processor capability has been increasing significantly, with increasingly faster and more powerful processors being utilized in computers, such as the PowerPC.RTM. processor from Motorola and the Pentium.RTM. processor from Intel. These processors may be programmed to perform a variety of functions.
Data communications devices ("DCDs") such as analog and digital modems, terminal adapters, and computer networking devices, generally have been utilized for data transfer between various DTEs over communications channels, such as the Public Switched Telephone Network ("PSTN") or Integrated Services Digital Network ("ISDN"). Such DCDs have typically been separate devices, such as desktop modems, rack-mounted modems, PCMCIA cards, or separate circuit boards utilized within a computer housing. In the prior art, moreover, such DCDs also typically contain several processors, such as a digital signal processor ("DSP") and a microprocessor, or a unitary processor combining the functions of both the DSP and the microprocessor. DCDs have tended to require separate processing capability because DCDs are computationally and mathematically intensive, performing such functions as modulation, demodulation, coding, decoding, data compression, error correction, precoding, equalization, interfacing with the DTE, and other control functions. In addition, DCDs have been performing at ever faster transmission rates, such as 28.8 kbps available under the V.34 standard (International Telecommunication Union ("ITU") Recommendation V.34), and with data compression and error correction protocols available under the ITU V.42 and V.42 bis standards. Such computationally intensive processing would tend to require more processor capability and more processing time than is generally available or desirable from a more general, multipurpose processor utilized in a DTE.
With the advent of increasing processor capability in DTEs, such as that available in the PowerPC.RTM. and Pentium.RTM. processors, the additional processing capability available in DCDs may no longer be necessary and may be redundant. Provided that such processing capability is available, it may be more cost effective and efficient to provide for a single processor, with appropriate hardware and software, capable of performing both the functions of the various computer applications programs, such as word processing, spreadsheets, mathematical computations and graphics, and the functions of a DCD, such as modulation, demodulation, and data compression. One such combined processor-DCD arrangement was disclosed in Blackwell et al.
U.S. Pat. No. 4,965,641, "Processor Modem", issued Oct. 23, 1990, and incorporated by reference herein.
With the increasing data transmission rates and other complex functions now required for DCDs which are to be compatible with the V.34 and V.42 bis protocols, implementations of a processor modem or other processor DCD may be complicated or difficult and may have increasing and potentially incompatible performance requirements. For example, a difficulty with the implementation of a processor modem is related to the high processing speeds available with the new, general purpose computer processors, which are capable of processing data for transmission at much faster rates than are typically available for actual data transmission over a channel. For example, the computer processor may be able to process data at rates in the megahertz or gigahertz range, which are several orders of magnitude greater than typical data transmission rates, such as 28.8 kbps for V.34 or 64 kbps for ISDN. Correspondingly, data may be arriving from a communications channel continually, at a specific and predetermined data transmission rate, which is typically much slower than the processing rate of the computer processor, and which may not effectively utilize the entire processing capability of the computer processor. For example, it would be an inefficient use of computer processor capability to have the processor waiting to receive data at 28.8 or 14.4 kbps, when the processor could be performing other application functions simultaneously. This mismatch or interface problem between data transmission rates and data processing rates tends to create a "bottleneck" problem, with either too much data available from the processor for transmission (given the data transmission rate), or too little data available from the channel for subsequent processing (given the computer processing capability). With other issues, this interface problem was addressed in the related application referenced above.
In addition, data transmission functions tend to be computationally intensive, potentially involving a tremendous number of calculations for digital signal processing, error control and correction, data compression, and various other modulation and demodulation functions. With such computationally intensive processes, currently available processor modems may not effectively or efficiently process other applications programs concurrently with data transmission. During data transmission, concurrent or simultaneous processing of other applications programs by such devices tends to be slow or to cease altogether, largely due to excessive computational loading of the processor during data transmission. In addition, typically such devices automatically provide for a maximum available data transmission rate, which may be unnecessary, may provide an excessive load to the processor, and may interfere with the simultaneous processing or concurrent operation of other applications. A need has remained, therefore, for an apparatus and method to provide for a balancing and optimizing of the various simultaneous or concurrent loads to the processor, to provide for concurrent operation of a communications application program (with corresponding data transfer over a communications channel), and operation of other applications programs, and to provide for both efficient data transfer and efficient use of processor capability.